What
As chip design complexity continues to scale, High-Level Synthesis (HLS) has become an essential methodology for accelerating hardware development and architectural exploration. Structured as a hands-on tutorial, this seminar provides a comprehensive guide to the end-to-end HLS workflow, bridging the gap between high-level algorithms and hardware realization.
We will walk participants step-by-step through three core phases of the design cycle:
- SystemC: Efficient hardware behavioral modeling and algorithm validation.
- Cadence Stratus: Translating high-level models into high-quality RTL code and executing design space exploration (DSE).
- Cadence Joules: Conducting precise, RTL-level power analysis and optimization evaluation.
When
29/1/2027 11:00 - 12:00
Where
ESAT Aula R
