Analog circuit sizing is still one of the most time-consuming steps in a chip design cycle due to numerous needed simulations, PVT variations, and conflicting required specifications. This seminar brings together two recent AI approaches that attack that bottleneck from different angles: AnaCraft — a model-based, adversarial reinforcement-learning (RL) approach that aims for PVT-robust, power/area-aware sizing with far fewer simulations — and AnaFlow — an agentic Large-Language-Model (LLM) workflow that automates circuit understanding, requirement interpretation, and iterative sizing refinement while producing human-readable reasoning.
17/10/2025 11:00 - 12:00
ESAT Aula L
