IGZO (InGaZnO)-DRAM has been increasingly explored as an alternative to traditional DRAM due to its reduced transistor leakage (~10-18A) and related minimal storage node capacitance in addition to ease of integration (entirely BEOL). The 2T0C IGZO-DRAM bit-cell configuration has additional benefits from a scaling point of view due to the potential for monolithic 3D stacking.
We present a 2T0C IGZO based Capacitor-less memory that enhances the sensing margin and retention time for DRAM applications requiring higher data immunity.
From our simulation results, the proposed scheme (termed as HVPC-RBL) demonstrates stronger data integrity on data ‘1’ without the need for any additional cell capacitor. An additional benefit is the higher SN level (> 2X) resulting in higher sensing speed (10X) allowing reduced parasitic cell capacitance requirement ~1aF. This is 1000X less than the ~ 1fF parasitic cell capacitance required at the storage node for the conventional VDD-precharged RBL scheme (VPC-RBL).
10/1/2025 11:00 - 12:00
ESAT Aula L
